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Published on Sep 20, 2019



Abstract

Hyper Transport technology is a high bandwidth solution for chip-to-chip communications it also has applications in other onboard technologies such as networking, telecommunications, Hyper Transport technology was designed to alleviate the I/O subsystem bottleneck found on computers today.

Description of Hyper Transport Technology


Hyper transport technology was designed to be an optimized board-level architecture delivering lowest possible latency, highest bandwidth, design flexibility, performance scalability and PCI compatibility. Hyper Transport technology is a high-bandwidth chip-to-chip inter connect technology that provides an integrated framework linking all core board-level functional units including processor, memory and I/O devices.

This makes it a powerful, high-performance board-level architecture for variety of product application and market segments. While Hyper Transport technology features protocol compatibility with traditional PCI (Peripheral Component Interconnect)buses, its 22.4 Gigabyte/second aggregate bandwidth provides the highest effective throughput available in a board-level interconnect technology and its Direct Packet protocols support the intermixing of traditional load/store traffic with communications-oriented user-packet based traffic.

As an optimized board-level architecture, Hyper Transport's advantages are many: the highest throughput of any standard interconnect solution, the lowest possible latency, scalable performance, standardized interfaces, simplified implementation, minimized software overhead, and the efficient intermixing of load/store traffic with packet-bus traffic.

The demand for faster processors, memory and I/O is a familiar refrain in market applications ranging from personal computers and servers to networking systems and from video games to office automation equipment. Once information is digitized, the speed at which it is processed becomes the foremost determinate of product success.