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Published on Feb 12, 2016

Abstract

During the last two decades, there has been an exponential growth in the operational speed of microprocessors. Also RAM capacities have been improving at more than fifty percent per year. However the speed and access time of the memory have been improving at slower rate. In order to keep up in performance and reliability with processor technology it is necessary to make considerable improvements in the memory access time. The Rambus founders emerged with a memory technology-RD RAM.

Description of RD RAM

RDRAM memory provides the highest bandwidth -2.1GB/sec. per pin- from the fewest pins at five-times the speed of industry available DRAM. The RDRAM memory channel achieves its high-speed operation through several innovative techniques including separate control and address buses, highly efficient protocol, low voltage signaling, and precise clocking to minimize skew between clock and data lines. A single RDRAM device is capable of transferring data at 1066Mb/sec. per-pin to Rambus-compatible ICs. Data rate per-pin will increase beyond 1066Mb/sec per pin in the future.

This technology is based on a very high-speed, chip-to-chip interface and has been incorporated into DRAM architectures called Rambus DRAM or RDRAM. It can also be used with conventional processors and controllers to achieve a performance rate that is 100 times faster than conventional DRAMs. At the heart of the Rambus Channel Memory architecture, is ordinary DRAM cells to store information. But the access to those cells, and the physical, electrical and logical construction of a Rambus memory system is entirely new and much, much faster than conventional DRAMs.

The Rambus channel transfers data on each edge of a 400 MHz differential clock to achieve an 800- MB/s data rate. It uses a very small number of very high speed signals to carry all the address, data and control information, greatly reducing the pin count and hence cost while maintaining high performance levels. The data and control lines have 800-mV logic levels that operate in a strictly controlled impedance environment and meet the specific high-speed timing requirements. This memory performance satisfies the requirements of the next generation of processors in PCs, servers, workstations as well as communications and consumer applications.

 

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