The demand for faster
processors, memory and I/O is a familiar refrain in market applications ranging
from personal computers and servers to networking systems and from video games
to office automation equipment. Once information is digitized, the speed at which
it is processed becomes the foremost determinate of product success. Faster system
speed leads to faster processing. Faster processing leads to faster system performance.
Faster system performance results in greater success in the marketplace. This
obvious logic has led a generation of processor and memory designers to focus
on one overriding objective - squeezing more speed from processors and memory
devices. Processor designers have responded with faster clock rates and super
pipelined architectures that use level 1 and level 2 caches to feed faster execution
units even faster. Memory designers have responded with dual data rate memories
that allow data access on both the leading and trailing clock edges doubling data
access. I/O developers have responded by designing faster and wider I/O channels
and introducing new protocols to meet anticipated I/O needs. Today, processors
hit the market with 2+ GHz clock rates, memory devices provide sub5 ns access
times and standard I/O buses are 32- and 64-bit wide, with new higher speed protocols
on the horizon.Increased processor speeds, faster
memories, and wider I/O channels are not always practical answers to the need
for speed. The main problem is integration of more and faster system elements.
Faster execution units, faster memories and wider, faster I/O buses lead to crowding
of more high-speed signal lines onto the physical printed circuit board. One aspect
of the integration problem is the physical problems posed by speed.
Hyper Transport
technology has been designed to provide system architects with significantly more
bandwidth, low-latency responses, lower pin counts, compatibility with legacy
PC buses, extensibility to new SNA buses, and transparency to operating system
software, with little impact on peripheral drivers.